As transistor semiconductor fabrication technology approaches the nanometer level, several primary advantages are realized by resulting circuits and systems that use them. Higher integration packs more features and functions into a given area of silicon than older fabrication technology, resulting in smaller and more easily portable devices. With higher integration, a larger number of chips per silicon wafer can be fabricated, effectively reducing the cost per chip. Smaller transistors switch faster due to a lowered threshold voltage, providing faster operating speed for systems.
An example of a semiconductor device that takes advantage of smaller dimensioned transistors is dynamic random access memory, simply referred to with the acronym DRAM from this point forward. Those of skill in the art understand that DRAM is most widely employed in computer systems due to its high density and speed. While there are different types of DRAM memory available to accommodate specific standards, such as RDRAM, SDRAM, DDR-SDRAM for example, their underlying core is still DRAM.
The DRAM memory cell is based on charge storage for differentiating between a stored logic “1” and logic “0”. Unfortunately, this charge will leak or dissipate after a relatively short period of time, hence requiring periodic refreshing to maintain the stored logic level. DRAM refresh is well known in the art, as are the circuits required to execute refresh operations. A simplified description of a refresh operation is now discussed with reference to the prior art DRAM system shown in FIG. 1.
The prior art DRAM of FIG. 1 includes a memory cell array 100, pitch-limited peripheral circuits, data path circuits, addressing circuits and refresh control circuits. The DRAM system of FIG. 1 has been simplified, however those skilled in the art will understand that DRAM systems will include other circuits to enable further functions.
The memory cell array 100 includes wordlines and bitlines coupled to memory cells. The pitch-limited peripheral circuits include row decoders 102 for driving the wordlines, and sense amplifier and bitline access circuits 104 for transferring data in to and out of the memory cells. Pitch-limited circuits are densely packed to correspond with the size of the memory cell array 100.
It is noted at nodes coupled or connected together can include links that may or may not include intervening circuits.
Addressing circuits can include a row address predecoder 106 for generating a predecoded row address in response to a row address R_ADDR[n], a column address decoders 108 for activating bitline access devices in response to a column address C_ADDR[m], and address buffers 110 for generating R_ADDR[n] and C_ADDR[m] in response to external addresses A0 to An. The data path circuits include data I/O circuits 112 for coupling the data between the sense amplifiers in block 104 to data input/output buffers (not shown). It is noted that variable n and m above are equal to 0 or integer values greater than 0.
The refresh control circuits include a command controller 114, an internal row address counter 116 and a self-refresh circuit 118. Such refresh control circuits are well known in the art, and the system shown in FIG. 1 can include additional circuit blocks to execute additional operations. Command controller 114 responds to clock signal CLK and receives several system level signals, such as CKE, WT, RD and REF, which are decoded to initiate various operations within the DRAM system through signal COMMAND. Three example operations used to illustrate the operation of the DRAM system will include a read operation, an auto-refresh operation and a self-refresh operation.
A DRAM read operation should be well known to those skilled in the art. In FIG. 1, a read operation is initiated when command controller 114 receives a predefined combination of signals CKE, WT, RD, REF to signal a read operation, and address buffer 110 receives a specific set of address signals A0 to An. Address buffer 110 generates a set of row addresses R_ADDR[n] and a set of column addresses C_ADDR[m]. Row address predecoder 106 generates predecoded row address signals from R_ADDR[n], which are then used by row decoders 102 to drive at least one wordline in memory cell array 100. All the memory cells connected to the driven wordline will couple their stored charge to respective bitlines. In other words, each bitline in memory cell array 100 will carry data, which is subsequently sensed and latched by corresponding bitline sense amplifiers in block 104. Depending upon the configuration, column address decoder 108 will select at least one bitline access device in block 104 corresponding to C_ADDR[m], to couple that bitline sense amplifier to data I/O circuit block 112. The read operation does not involve the refresh control circuits.
The main difference between an auto-refresh and a self-refresh operation is the time they are executed. Auto-refresh, also known as CAS-Before-RAS refresh and RAS-Only refresh, is executed during normal operation of the DRAM system, while a self-refresh operation is executed during a sleep mode of the DRAM system. It is well known that a sleep mode is used to power down selected circuits of the DRAM system in order to reduce power consumption, however DRAM cells in memory cell array 100 must be refreshed during sleep mode to retain the stored data.
An auto-refresh operation is executed during normal operation of the DRAM system when a refresh command is received via the external signals received by command controller 114. The command controller 114 then provides a control signal REFR to increment or decrement internal row address counter 116, and to enable latching by the address buffers 110. Internal row address counter 116 provides a refresh address REF_ADDR[p] which is latched by address buffers 110. It is noted that variable p is equal to 0 or an integer value greater than 0. Address buffers 110 generates a row address R_ADDR[n], which is decoded by row address predecoder 106 and row decoders 102 to drive at least one wordline. Each bitline sense amplifier then restores the charge of the accessed memory cells through its inherent amplifying operation. Since the auto-refresh operation is executed during normal operation with priority over other operations, it is executed quickly to allow other operations to resume.
The self-refresh circuit 118 includes an internal oscillator (not shown). The DRAM system enters sleep mode (or “self-refresh mode”) through the command controller 114 to initiate the oscillator of the self-refresh circuit 118. Self-refresh circuit 118 provides a sleep signal SLEEP for internal row address counter 116. In accordance with the commands for self-refresh entry and exit, a signal OSC_OUT is periodically generated in the self-refresh mode. The generated signal OSC_OUT is provided to internal row address counter 116 and address buffers 110. In response to OSC_OUT, address buffers 110 latches REF_ADDR[p] generated by internal row address counter 116, and provides row address R_ADDR[n]. As in the previously described auto-refresh case, a wordline is driven via row address predecoder 106 and row decoders 102 to refresh the memory cells in memory cell array 100.
Implementation of the DRAM system of FIG. 1 in state of the art nanometer fabrication technology will inherently increase the speed performance of the system. In particular the transistors, especially the row address predecoder 106 and row decoders 102, can be optimized to minimize propagation delay of the row address R_ADDR[n] through them. However, a significant disadvantage of minimally dimensioned high-speed transistors is leakage current through the transistor, which increases the overall power consumption of the DRAM system. Current leakage problems with nanometer scale technology has been well documented by the semiconductor industry. Therefore, the high-speed operation is obtained at the expense of power consumption.
FIGS. 2 and 3 are circuit schematics presented to illustrate the source of current leakage in nanometer technology transistors. FIG. 2 is a simple logic gate circuit consisting of a 2-input NAND gate 200 having an output connected to an input of an inverter 202. By example, this circuit can be one of several circuits in the row address predecoder 106 of FIG. 1. NAND gate 200 receives two row addresses, R_ADDR[h] and R_ADDR[i], and generates predecoded row address PDR_ADDR[k] through inverter 202. It is noted that variables h, i and k are equal to 0 or integer values greater than 0. Both NAND gate 200 and inverter 202 are implemented with CMOS transistors, and preferably minimally sized to maximize speed. While not explicitly shown, the two logic gates are connected to the VDD and VSS power supplies. Current leakage can occur in all the transistors of each logic gate, as will be shown in FIG. 3.
FIG. 3 is a transistor schematic of inverter 202 shown in FIG. 2. Inverter 202 is a standard complementary CMOS inverter consisting of p-channel transistor 300 and n-channel transistor 302 connected in series between VDD and VSS. The CMOS transistor implementation of NAND gate 200 is well known in the art and hence not shown. When implemented in nanometer technology, transistors 300 and 302 can leak current (Ileak1) from VDD to VSS even if input signal IN is held at the logic “0” or logic “1” states. Furthermore, current can leak from VDD through the thin gate oxides of transistors 300 and 302 (Ileak2), allowing current to flow through to a drain/source terminal of a preceding transistor. For example, if the gate of transistor 300 is driven to VSS by a preceding circuit, current can leak from VDD through its gate oxide directly to VSS.
Therefore, self-refresh operations for DRAM systems can consume a significant amount of power, which is undesirable for portable computing applications. In portable computing applications where battery life is finite, the sleep mode can be frequently used and for extended periods of time in an effort to extend battery life.
It is, therefore, desirable to provide a low power self-refresh scheme for DRAM systems.